1. Field of the Invention
The present invention relates to a selection method of bit line redundancy repair and an apparatus performing the same, and more particularly, to a selection method of bit line redundancy repair with flexible repair capability and an apparatus performing the same.
2. Description of the Related Art
After the manufacturing of semiconductor memory devices, various tests are conducted to determine whether or not the circuits on the semiconductor memory devices operate in conformity with predetermined specifications. Multiple test parameters are used in each test to check the electrical properties and operation of the circuits. When any of the circuits within the semiconductor memory device is found to have a defect, a remedial measure for such a defect for the semiconductor memory device may not be possible. If a portion of normal memory cells is determined to be in a defective state, then such portion of the memory cells can be replaced with a redundant memory cell so that the semiconductor memory device can operate normally. In other words, to correct the defect, a redundancy circuit including fuses that are meltable by a high-energy light such as laser etc., is fabricated together with the memory cell and circuit devices of the semiconductor memory devices during its manufacturing process.
In U.S. Pat. Publication No. US2005/0207244, herein incorporated by reference and hereinafter '244, a semiconductor memory device 1 carrying out redundancy repair is disclosed, as shown in FIG. 1. The semiconductor memory device 1 includes a normal cell array 11, a redundant cell array 12, a cell drain selection circuit 13, a column decoder circuit 14, a defective cell block column redundancy selection circuit 15, an adjacent cell block column redundancy selection circuit 16, and a row decoder circuit 18. FIG. 2 shows a circuit diagram of the normal and redundant cell arrays in FIG. 1. The normal cell array 11 has 16×8 memory cell transistors, sixteen of which (ML0, MR0, ML1, MR1 . . . ML7, MR7) receive word line select signal WL1. Current is supplied to the normal cell array 11 through memory cell drain select transistors MDSL0, MDSL1 . . . MDSL7; data signals are read out through column switch transistors MBL0, MBL1 . . . MBL7. In the normal cell array 11, normal cells ML2, MR2, ML3, MR3 and other normal cells in the same columns constitute one cell block 110. Similarly, normal cells MLO, MR0, ML1, MR1 and other normal cells in the same columns constitute another cell block; normal cells ML4, MR4, ML5, MR5 and other normal cells in the same columns constitute still another cell block; normal cells ML6, MR6, ML7, MR7 and other normal cells in the same columns constitute yet another cell block (the columns including cells ML5, MR5, ML6, MR6, and ML7 are not shown). The redundant cell array 12 includes 8×8 redundant cells containing redundant memory cell transistor (redundant cells), eight of which (RML0, RMR0, RML1, RMR1 . . . , RML3, RMR3) receive word line select signal WL1. Current is supplied to the redundant cell array 12 through redundant memory cell drain select transistors RMDSL0, RMDSL1, RMDSL2 . . . RMDSL4; data signals are read out through redundant column switch transistors RMBL0, RMBL1 . . . RMBL3. In redundant cell array 12, redundant cells RML0, RMR0, RML1, RMR1 and other redundant cells in the same redundant columns constitute a first redundant cell block 120 for replacing a defective cell block (e.g., cell block 110) in the normal cell array 11. Redundant cells RML2, RMR2, RML3, RMR3 and other redundant cells in the same columns constitute a second redundant cell block 121 for replacing a non-defective cell block adjacent to the defective cell block. More accurately, one or two non-defective half-blocks can be replaced. For example, if cell block 110 is defective, the memory cells in redundant cell block 121 may be used to replace adjacent half-block 111 (located to the left of cell block 110), adjacent half-block 112 (located to the right of cell block 110), or both adjacent half-blocks 111 and 112.
FIG. 3 shows an exemplary circuit structure of the defective cell block column redundancy selection circuit 15 in FIG. 1, which generates the column select signals RY0 and RY1 for the first redundant cell block 120. The defective cell block column redundancy selection circuit 15 includes three fuse-programmable circuits 150-152, two address selection circuits 153 and 154, and an address decoding circuit 155. The fuse-programmable circuit 150 generates a redundancy enable signal FMAIN that is programmed to the high logic level when redundancy repair is necessary and to the low logic level when redundancy repair is not necessary. When redundancy repair is necessary, the fuse-programmable circuits 151 and 152 store the address of the defective cell block. The fuse-programmable circuits 150-152 have identical structures, each including a resistor and a fuse. In the fuse-programmable circuit 150, for example, one end of the resistor R50 is connected to a power supply node Vcc, one end of the fuse F50 is connected to the other end of the resistor R50, and the other end of the fuse F50 is connected to a ground node. The redundancy enable signal FMAIN is outputted from a node at which the resistor R50 and the fuse F50 are interconnected. A fuse-programmable address signal FY2 is outputted from a node at which the resistor (not shown) and the fuse (not shown) in the fuse-programmable circuit 151 are interconnected. Another fuse programmable address signal FY3 is outputted from a node at which the resistor (not shown) and the fuse (not shown) in the fuse-programmable circuit 152 are interconnected. The address selection circuits 153 and 154 are identically structured as exclusive-NOR (EXNOR) gates, each including a pair of inverters I50, I51 and a pair of MOS switches M50 and M51. Each address selection circuit 153 (or 154) compares one address bit AY2 (or AY3) with one fuse programmable address signal FY2 (or FY3) and generates a redundant column address signal FA2 (or FA3). The redundant column address signal FA2 (or FA3) is high if the address bit AY2 (or AY3) and fuse programmable address signal FY2 (or FY3) have the same logic levels, and low if they have different logic levels. Therefore, the column select signal RY0 or RY1 is actuated to the high logic level to initiate the bit line redundancy repair only when the fuse programmable address signal FY2 (or FY3) and the address bit AY2 (or AY3) have the same logic level, and the redundancy enable signal FMAIN has the high logic level according to the defective cell block column redundancy selection circuit 15 in FIG. 3.
FIG. 4(a) shows a schematic representation of the circuit structure of the defective cell bock column redundancy selection circuit 15 in FIG. 3. FIG. 4(b) shows a similarly schematic representation of the circuit structure of the adjacent cell block column redundancy selection circuit 16 in FIG. 1. The adjacent cell block column redundancy selection circuit 16 includes fuse-programmable circuits 156, 157, adjacent address generating circuits 160, 161, 162, 163, 164, 165, address selection circuits 166, 167, 168, 169, 170, 171, and address decoding circuits 172, 173. The fuse-programmable circuit 156, the adjacent address generating circuits 160, 161, 162, the address selection circuits 166, 167, 168, and the address decoding circuit 172 constitute an upper column redundancy selection circuit 174; the fuse-programmable circuit 157, the adjacent address generating circuits 160, 161,162, the address selection circuits 163, 164, 165, and the address decoding circuit 173 constitute a lower column redundancy selection circuit 175. The upper and lower column redundancy selection circuits 174 and 175 generate an upper redundant column selection signal RYU and a lower redundant column selection signal RYD to select the left half and the right half of the redundant cell blocks 121 to replace the normal adjacent half-blocks 112 and 111, respectively.
To achieve the replacement of the defective cell block 110 and two adjacent half-blocks 111 and 112, the defective cell block column redundancy selection circuit 15 and the adjacent cell block column redundancy selection circuit 16 are required. That is, nine fuses (three fuses in each of the defective cell block column redundancy selection circuit 15, the upper column redundancy selection circuit 174 and the lower column redundancy selection circuit 175) are required to implement the bit line redundancy repair. Consequently, a large area for these fuses is occupied in the semiconductor device, especially in the NAND flash application, which needs large amount of redundancy (around 1%-2% redundancy bit line) to maintain acceptable product yield.